High-speed ADC PCB layout techniques

In high-speed analog signal chain design, printed circuit board (PCB) layout requires consideration of many options. Some options are more important than others, and some options depend on the application. The final answer is different, but in all cases, the design engineer should try to eliminate the error of the best practice, not to over-calculate every detail of the layout and wiring. Here is an article written by Rob Reeder, an experienced system application engineer at ADI, "High Speed ​​ADC PCB Layout and Wiring Tips." An article written by Rob Reeder**** believes this article will be helpful to everyone's high-speed design projects.

Exposed pad

The exposed pad (EPAD) is sometimes overlooked, but it is very important for the performance of the signal chain and adequate heat dissipation of the device.

The exposed pad, which Analog Devices calls pins 0, is the pad under most of today's devices. It is an important connection where all internal ground of the chip is connected to the center point below the device. I wonder if you have noticed that the lack of ground pins in many converters and amplifiers today is due to the exposed pad.

The key is to properly secure (ie, solder) this pin to the PCB for reliable electrical and thermal connections. If this connection is not firm, there will be confusion. In other words, the design may not work.

Make the best connection

There are three steps to using the exposed pad to achieve the best electrical and thermal connections. First, if possible, the exposed pad should be replicated on each PCB layer. The purpose of this is to form a dense thermal connection with all ground and ground planes for rapid heat dissipation. This step is related to high power devices and applications with a high number of channels. Electrically, this will provide good equipotential bonding for all ground planes.

It is even possible to replicate the exposed pad on the bottom layer (see Figure 1), which can be used as a decoupling heat sink ground and where the bottom side heat sink is mounted.

Second, divide the exposed pad into multiple identical parts, like a chessboard. Use a screen cross grid on the exposed exposed pad, or use a solder mask. This step ensures a solid connection between the device and the PCB. In the reflow assembly process, it is impossible to determine how the solder paste flows and ultimately connect the device to the PCB.

Connections may exist but are unevenly distributed. You may only get one connection, and the connection is small, or worse, at the corner. Dividing the exposed pad into smaller sections ensures that each area has a connection point for a more rugged, uniformly connected exposed pad (see Figure 2 and Figure 3).

Finally, you should make sure that all parts have vias connected to ground. Each area is usually large enough to place multiple vias. Before assembly, be sure to fill each via with solder paste or epoxy resin. This step is very important to ensure that the exposed pad solder paste will not reflow into these via holes and affect proper connection. Finally, you should make sure that all parts have vias connected to ground. Each area is usually large enough to place multiple vias. Before assembly, be sure to fill each via with solder paste or epoxy resin. This step is very important to ensure that the exposed pad solder paste will not reflow into these via holes and affect proper connection.

Decoupling and layer capacitance

Sometimes engineers ignore the purpose of using decoupling, and only distribute a lot of capacitors of different sizes on the board, so that the lower impedance power supply is connected to ground. But the problem remains: how much capacitance is needed? Many related literature indicate that many capacitors of different sizes must be used to reduce the power transmission system (PDS) impedance, but this is not entirely correct. Conversely, simply selecting the correct size and type of capacitor can reduce the PDS impedance.

Consider designing a 10 mΩ reference layer as shown in Figure 4. As the red curve shows, many different values ​​of capacitance are used on the system board, 0.001 μF, 0.01 μF, 0.1 μF, and so on. This of course can reduce the impedance in the 500 MHz frequency range, but look at the green curve. The same design uses only 0.1 μF and 10 μF capacitors. This proves that if you use the correct capacitor, you don't need so much capacitance. This also helps to save space and material (BOM) costs.

Note that not all capacitors are “born equally”, even if the same supplier has different processes, sizes, and styles. If the correct capacitor is not used, whether it is multiple capacitors or several different types, it will have a negative effect on the PDS.

The result may be an inductive loop. Improper placement of capacitors or use of different processes and types of capacitors (and therefore different responses to the frequencies within the system) may cause resonances between each other (see Figure 5).

It is important to understand the frequency response of the type of capacitor used by the system. The choice of capacitors will make it harder to design low-impedance PDS systems.

PDS high-frequency layer capacitance

To design a qualified PDS, you need to use a variety of capacitors (see Figure 4). The typical capacitance used on the PCB can only reduce the impedance of the DC or near-DC frequency to about 500 MHz. Above 500 MHz, the capacitance depends on the internal capacitance formed by the PCB. Note that close overlap of the power plane and ground plane will help.

A PCB stack structure that supports larger layer capacitors should be designed. For example, a six-layer stack may include a top signal layer, a first ground plane, a first power plane, a second power plane, a second ground plane, and a bottom signal layer. It is specified that the first ground layer and the first power layer are close to each other in the stacked structure, and the two layers have a pitch of 2 to 4 mils to form a natural high-frequency layer capacitance. The biggest advantage of this capacitor is that it is free, just specify in the PCB manufacturing notes. If you have to split the power plane and there are multiple VDD power rails on the same layer, use as large a power plane as possible. Do not leave empty holes and pay attention to sensitive circuits. This will maximize the capacitance of the VDD layer.

If the design allows additional layers (in the example above, from six to eight layers), two additional ground planes should be placed between the first and second power planes. In the case where the core pitch is also 2 to 3 mils, the intrinsic capacitance of the laminated structure will be doubled at this time (see Fig. 6 for an example).

This structure is easier to design than adding more discrete high frequency capacitors to keep the impedance low at high frequencies.

The task of the PDS is to minimize the voltage ripple generated in response to the supply current demand, which is important but often overlooked. All circuits need current, some circuits require more, and some circuits need to provide current at a faster rate. The use of fully decoupled, low-impedance power planes or ground planes, and good PCB stackups help minimize voltage ripple due to circuit current requirements. For example, depending on the decoupling strategy used, if the system design has a switching current of 1 A and the PDS impedance is 10 mΩ, the maximum voltage ripple is 10 mV. The calculation is simple: V = IR.

With a perfect PCB stack, it can cover the high frequency range while using conventional decoupling around the power entry starting point and high power or inrush current devices to cover the low frequency range (<500 MHz). This ensures that the PDS impedance is lowest across the entire frequency range. It is not necessary to configure the capacitors everywhere; the placement of the capacitors against each IC destroys many manufacturing rules. If such drastic measures are needed, there are other problems with the circuit. Layer coupling

Some layouts inevitably have overlapping circuit layers (see Figure 8). In some cases, it may be a sensitive analog layer (such as power, ground, or signals), and the lower layer is a high-noise digital layer.



This is often overlooked because the high-noise layer is in another layer - below the sensitive simulation layer. However, a simple experiment can prove that this is not the case. Taking a certain level as an example, signals are injected at any layer. Then connect another layer and cross-couple this adjacent layer to the spectrum analyzer. The amount of semaphores coupled to adjacent layers is shown in Figure 8. Even though the distance is 40 mils, it is still a capacitance in some sense, so at some frequencies it will still couple signals to adjacent layers.

An example of this is shown. For example, suppose a high-noise digital layer on one level has a high-speed switching 1 V signal. This means that the other layer will see a 1 mV coupling (approximately 60 dB isolation). For a 12-bit ADC with a 2-V pp full-scale swing, this is a 2 LSB coupling. This may not be a problem for a particular system, but it should be noted that if the sensitivity of the system is increased by two bits, from 12 bits to 14 bits, the sensitivity of this coupling will only increase by a factor of four, ie 8 LSBs.

Ignoring this type of cross-layer coupling may invalidate the system or weaken the design. It must be noted that the coupling between the two layers may be beyond imagination.

This should be taken into account when noise spurious coupling is found within the target spectrum. Sometimes the layout determines unintended signals or layers should be cross-coupled to different layers. Also, be aware of this when debugging sensitive systems. This problem may appear on the following layer.

Separate ground

The question most frequently asked by analog signal chain designers is: Should the ground plane be divided into AGND and DGND ground planes when using an ADC? The simple answer is: as the case may be.

The detailed answer is: usually not separated. Why not? Because in most cases, blindly separating the ground plane will only increase the inductance of the return path, it will bring more harm than good.

From the formula V = L(di/dt), it can be seen that the voltage noise increases as the inductance increases. As the inductance increases, the PDS impedance the designer tries to push down increases. As the need to increase the ADC sampling rate continues to increase, the way to reduce the switching current (di/dt) is limited. Therefore, keep these ground connections unless you need to separate the ground planes.

The key is that the circuit segmentation should be reasonable, so there is no need to separate the ground plane, as shown in Figure 9. Note that if the layout allows you to keep the circuit in its own area, there is no need to separate the ground plane. This division provides star grounding, confining the return current to specific circuit sections.

Due to the size limitation, when the circuit board cannot achieve a good layout split, it is necessary to separate the ground plane. This may be to meet traditional design requirements or dimensions, and dirty bus power or high noise digital circuits must be placed in certain areas. In this case, separating the ground plane is the key to good performance. However, for the overall design to be effective, these ground planes must be connected together somewhere in the board through a bridge or connection point. Therefore, the connection points should be evenly distributed on separate ground planes.

Eventually, there will often be a connection point on the PCB that will be the best place for the return current to pass without degrading the performance or forcing the return current into the sensitive circuit. If this connection point is located near, in or near the converter, there is no need to separate the ground.

Due to too many best options, layout considerations are always confusing. Technology and principles have always been part of the company's design culture. Engineers like to learn from the experience of previous designs. At the same time, the pressure to market makes designers unwilling to change or try new technologies. They stick to risk trade-offs until major problems arise in the system.

Simple single grounding is the best at the board, module, and system level. Good circuit segmentation is the key. This also affects the layout of layers and adjacent layers. If the sensitive layer is above the high noise digital layer, be aware that cross-coupling may occur. Assembly is also important; manufacturing notes provided to the PCB workshop or assembly shop should be used to ensure a reliable connection between the exposed exposed pad of the IC and the PCB.

Poor assembly often leads to poor system performance. Decoupling close to the power plane entry point and the VDD pin of the converter or IC is always advantageous. However, in order to increase the inherent high-frequency decoupling capacitance, close stacked power and ground planes should be used (pitch ≤ 4 mils). This method does not bring additional costs. It takes only a few minutes to update the PCB manufacturing notes.

When designing high-speed, high-resolution converter layouts, it is difficult to take care of all the specific features. Each application is unique. I hope that the points outlined in this application note will help design engineers better understand future system designs.