There are currently two main trends in the structure of mobile terminals. One is to face the ever-changing standards, emphasizing the flexibility of using programmable DSP; the other is to emphasize the high efficiency realized by application specific integrated circuit (ASIC). In the future, these two aspects will be combined. Application of DSP in GSM The functional block diagram of GSM is shown in Figure 1. A typical digital communication module in the figure includes: signal compression, error detection, encryption, modulation and equalization. In GSM phase 1, the encoder uses short pulse excitation linear pre-warming coding technology to compress the voice to 13Kb / s. Most hardware engineers think that the voice encoder should be implemented by DSP. Now DSP in the functional diagram shown in Figure 1, began to assume other functions of the physical layer. Flexibility is very important in the evolving standards. Enhanced full rate (EFR) and half rate (HR) voice coding was introduced in GSM Phase 2. The half rate achieves the same voice quality, and the compression rate is higher, reaching 5.6Kb / s, but at the cost of increased complexity. Enhancing the full rate can provide better voice quality and performance at the cost of higher complexity. It is implemented using an algorithm called vector and excited linear prediction (VSELP). With these changes, the performance of the physical layer is getting better and better, the cost is getting lower and lower, and the power is more saving. Therefore, the physical layer of each generation of mobile terminals has some slight differences from the previous generation, and the upgrade of ASIC-based solutions is more difficult and costly. Because there are now low-power DSPs specifically designed for wireless applications, the power savings achieved by using ASICs to implement the functions done by DSPs are not enough to allow system designers to give up the flexibility of DSP design. With the evolution of the GSM mobile terminal, it has gradually evolved to not only implement simple telephone functions, which makes it possible to use DSPs not only at the physical layer but also at other layers. Especially with the arrival of the third generation of mobile communications and the application of wireless data services, this trend will accelerate. The trend of DSP towards low power consumption The enhanced structure, design, and processing capabilities of the new generation of DSPs provide better performance and lower power consumption, making them suitable for battery-powered applications. We know that many communication algorithms are multiply and accumulate (MuAcc) operations. So we use mW per million MuAcc to evaluate the power consumption of DSP. According to statistics, the current DSP power consumption is reduced by half every 18 months. Due to the static logic used by the DSP, the main power consumption is to charge and discharge the internal capacitance of the device. This dynamic power consumption is as follows: p = ac & TImes; V swing & TImes; V power supply & TImes; f In the above formula, P represents the power consumed, a represents the number of internal nodes in each clock cycle, v swing is equal to v power supply, and f represents frequency. The dynamic power consumption of the entire chip is the sum of P of all nodes in the circuit. As can be seen from the above formula, since the dynamic power consumption of each node is proportional to the square of the power supply voltage, it is important to reduce the power supply voltage to save power. However, simply reducing the supply voltage without improving the technology is imperfect. Therefore, it is necessary to improve the technology while reducing the supply voltage to improve performance and reduce power consumption. Below we take TI's TMS320C54x as an example to introduce its low power consumption design. TMS320C54x is a DSP chip specially designed for wireless communication applications. In addition, as the wireless market continues to grow, several other DSP chips specifically designed for wireless applications have appeared on the market. The structure and instruction set of the C54x are designed to save power. C54x uses an improved Harvard architecture with three data storage buses, a program storage bus, two data address generators, and a program address generator. This structure makes it possible to access numbers at the same time, which is suitable for multi-operand operations, thereby reducing the cycle time required to complete the same function. Another strategy for C54x to save power is to add special instructions that can execute important algorithms in wireless applications. There is also a comparative selection storage unit (CSSU) that greatly accelerates the speed of Viterbi decoding. The C54x instruction set also contains several special instructions, including: single instruction repetition and instruction block repetition, conditional instructions, Euclidean distance calculation, FIR (finite impulse response) and LMS (least mean square) filter operation instructions. All in all, it is convenient to consume 7.4mW power when using DSP to complete VSELP in IS-54 / 136 standard, and 1.3mW power when GSM voice coding. Power management is very important in low-power DSP. C54x applies a hybrid power management strategy, that is, Lou Huo's internal clock control and three user control idle modes: turn off the CPU, turn off the CPU and on-chip peripherals, and only keep memory The state of the entire device is closed. The combination of a clock generator based on a digital phase-locked loop and a northern method allows the user to optimize the frequency and power consumption of the application. Future applications and structures of mobile energy devices There have been several development trends in cellular communication since its commercial use in 1983, the most important being the development from analog to digital, which has increased the capacity of the system and the number of users, which has driven the demand for powerful DSPs. The dual-processor architecture for traditional cellular phones is actually a simple modem. In the future, data-based terminals will have a new structure. It must increase processing resources to support increasingly complex user interfaces and handle more complex data services and more complex application environments besides voice. Among them, one solution is a DSP core plus coprocessor structure, and another structure is multiple DSPs plus additional hardware to accelerate complex processing. In short, low-power DSP will be more widely used in future mobile communications.
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