Clock signal and address arrive at the receiving end at the same time, simulate specific waveform analysis
Wiring plays a crucial role in electronic design. The key to achieving a successful design lies in ensuring that the system has enough timing margin. To maintain proper timing, line length matching is an essential technique. Let’s revisit the basic principles of wiring: address, control/command signals, and clock signals should be matched in length. Data signals, on the other hand, should match the DQS signal in length. Why is this important? Because signals within the same group must arrive at the receiver at the same time, allowing the receiving chip to process them simultaneously. But what happens when the clock and address signals arrive at the same time? How do their waveforms align? Let's look at the simulation results.
We set up a simulation to analyze the address and clock signals. The setup is shown in Figure 1. For simplicity, we assume a DDR clock frequency of 500MHz, which corresponds to an address signal rate of 500Mbps. Although DDR is double data rate, the address and control signals are still single-speed. Now, let's examine the waveform. When the address and clock lines are equal in length, the received waveforms are as shown in Figure 2. Red represents the address signal, and green represents the clock signal.
From Figure 2, it's not immediately clear how the clock and address signals relate in timing. By viewing the eye diagram, the setup and hold times become more apparent. As shown in Figure 3, the setup time is approximately 891ps, and the hold time is around 881ps. This is the waveform when the address and clock signals are perfectly matched.
Now, let's consider what happens if the address line is 200ps slower than the clock line. The resulting eye diagram is shown in Figure 4. In this case, the hold time decreases to 684ps, while the setup time increases to 1.1ns. This shows that when the address line is longer than the clock line, the setup time becomes shorter. Similarly, if the clock line is longer, the setup time increases, but the hold time decreases.
Now, let's look at the double-rate data signals. The simulation setup for DQ and DQS is shown in Figure 5. The driver and receiver models are from a chip manufacturer. The simulation waveforms are displayed in Figure 6. We then generate an eye diagram for both DQ and DQS signals, as shown in Figure 7.
In the eye diagram, you might notice that the edges of the data and clock signals appear aligned. However, this is due to the fact that the transmission paths for DQ and DQS are the same length. In reality, the master chip adjusts the timing so that the data signal is released a quarter cycle earlier than the DQS signal. The actual waveform at the receiver should look like Figure 8, where the DQS edge aligns with the center of the DQ bit, ensuring sufficient setup and hold time.
If the lengths of DQ and DQS are not matched, the DQS edge will not be centered on the DQ signal, reducing the timing margin. As shown in Figure 9, any delay deviation between the clock and data signals can affect the timing parameters, making the setup time margin smaller.
To better understand this, let’s look at a practical example using the Freescale MPC8572 DDR controller. The timing diagram and parameters are shown in Figures 10 and 11. On the receiver side, we have a Micron DDR chip, whose timing requirements are illustrated in Figure 12.
The delay skew between DQ and DQS (T_pcbskew) must satisfy certain conditions to ensure enough timing margin:
T_pcbskew > T_vb - T_setup
T_pcbskew < T_hold - T_va
Substituting values, we get:
T_vb - T_setup = 375 - 215 = 160ps
T_hold - T_va = -160ps
Assuming a transmission speed of 6 mil/ps, the allowable skew is ±960 mil. While this seems large, it doesn’t account for factors like clock and data jitter, crosstalk, or intersymbol interference. These real-world issues reduce the available margin significantly.
In conclusion, the main goal of timing control is to ensure that the data has enough setup and hold time at the receiver. Understanding these concepts allows engineers to confidently handle layout and matching challenges during the design process.
Recreational Vehicle Battery,Bms Rechargeable Rv Battery,Camping Rechargeable Battery,Golf Cart Battery
JIANGMEN RONDA LITHIUM BATTERY CO., LTD. , https://www.ronda-battery.com