66 common problems in high frequency PCB circuit design
With the rapid development of electronic technology and the widespread application of wireless communication in various fields, high frequency, high speed, and high density have gradually become significant trends in modern electronics. High-frequency signal transmission and high-speed digitization push PCBs toward micro-vias, buried/blind vias, fine lines, and uniform thinning of dielectric layers. High-frequency, high-speed, and high-density multilayer PCB design has become a key research area. Based on years of experience in hardware design, the author summarizes some design techniques and precautions for high-frequency circuits for your reference.
1. How to choose PCB boards?
Choosing the right PCB material involves balancing design requirements with mass production and cost. Design needs include both electrical and mechanical aspects. This is especially important when designing very high-speed PCBs (above GHz). For example, FR-4 material can cause significant signal attenuation at several GHz due to dielectric loss, making it unsuitable. Electrical considerations require attention to the dielectric constant and loss at the designed frequency.
2. How to avoid high-frequency interference?
The main idea is to minimize electromagnetic interference from high-frequency signals, known as crosstalk. You can increase the distance between high-speed and analog signals or add ground guard/shunt traces next to analog signals. Also, be cautious about digital ground noise affecting the analog ground.
3. How to solve signal integrity issues in high-speed design?
Signal integrity primarily concerns impedance matching. Factors like the source architecture, output impedance, trace characteristic impedance, load characteristics, and trace topology influence this. Solutions involve termination and adjusting the trace topology.
4. How is differential wiring implemented?
For differential pairs, two points are crucial: the two lines should be as long as possible, and their spacing (determined by differential impedance) must remain consistent, meaning they should be parallel. There are two ways to do this: side-by-side or top-by-side. Side-by-side is more common.
5. How to implement differential routing for a clock signal with only one output?
Differential routing requires both the source and receiver to use differential signals. Therefore, it cannot be applied to a clock signal with only one output.
6. Can a matching resistor be added between differential pairs at the receiving end?
Yes, adding a matching resistor at the receiving end of differential pairs is common. Its value should match the differential impedance, which improves signal quality.
7. Why is the wiring of differential pairs close and parallel?
Proper proximity ensures the correct differential impedance, a key parameter for differential pair design. Parallelism maintains consistent differential impedance. If the lines are too close, the differential impedance may vary, affecting signal integrity and timing delay.
8. How to deal with theoretical conflicts in actual wiring?
Generally, isolating analog and digital partitions is essential. Avoid having signal traces cross the moat, and keep the return current path of power and signals small.
9. How to resolve conflicts between manual and automatic routing for high-speed signals?
Most autorouters have constraints to control routing methods and via count. However, EDA companies’ routing engines may not always meet all requirements. For instance, controlling serpentine routing or differential pair spacing can affect whether the automatically routed method meets the designer’s expectations. Manual adjustment difficulty also depends on the routing engine's capabilities, such as line pushing, hole pushing, and copper pushing. Choosing a router with a strong routing engine is the solution.
10. About test coupons.
Test coupons measure PCB characteristic impedance using TDR (Time Domain Reflectometer) to meet design requirements. The trace width and spacing (for differential pairs) on the coupon should match those of the controlled trace. The grounding point position during measurement is critical. To reduce ground lead inductance, the TDR probe is grounded close to the probe tip, ensuring the signal measurement point and ground point on the coupon match the probe used.
11. In high-speed PCB design, can the blank areas of the signal layer be coated with copper, and how should the copper on multiple signal layers be distributed over the ground and power supply?
Most copper in blank areas is grounded. Be careful about the distance between the copper and high-speed signal lines, as applying copper can reduce the trace's characteristic impedance. Also, ensure that the copper does not affect the characteristic impedance of its layer, such as in a dual strip line structure.
12. Can the characteristic impedance be calculated using the microstrip line model on the signal line above the power plane? Can the signal between the power and ground planes be calculated using the stripline model?
Yes, both the power and ground planes must be considered as reference planes when calculating characteristic impedance. For example, in a four-layer board (top layer - power layer - ground layer - bottom layer), the top trace's characteristic impedance model is a microstrip line with the power plane as the reference.
13. Can software automatically generate test points for high-density PCBs, and will it meet mass production testing requirements?
Whether the general software can automatically generate test points depends on whether the test point specifications meet the equipment requirements. If the wiring is too dense and the test point specifications are strict, there may be no way to automatically add test points to each line. Manual filling of test points may be necessary.
14. Does adding test points affect the quality of high-speed signals?
It depends on how the test points are added and the signal speed. Adding test points without vias or DIP pins may involve adding a small capacitor on the line or a short branch. Both can impact high-speed signals, with the degree of influence related to the signal frequency and edge rate. Simulation can help determine the impact. Smaller test points and shorter branches are better.
15. How many PCBs form the system, and how should the ground wires between the boards be connected?
When connecting signals or power between PCBs, the current returning from the ground must be equal to the current flowing out. This current will take the path of least impedance. At each interface where power or signals are connected, the number of ground pins should not be too small to reduce impedance and ground noise. Analyze the entire current loop, especially large currents, and adjust the ground or connection to control the current path.
16. Are there any foreign technical books and data on high-speed PCB design?
High-speed digital circuits today are used in communication networks and calculators. Communication networks operate at GHz frequencies with up to 40 layers. Calculator-related applications are also driven by chip advancements. Whether it's a general PC or server, the maximum operating frequency on the board has reached 400MHz (such as Rambus). These design requirements are available to manufacturers in large quantities.
17. Two commonly referenced characteristic impedance equations:
Microstrip Z = {87 / [sqrt(Er + 1.41)]} * ln[5.98H / (0.8W + T)], where W is the line width, T is the copper thickness, H is the distance from the trace to the reference plane, and Er is the dielectric constant of the PCB material. This formula applies when 0.1 < (W/H) < 2.0 and 1 < (Er) < 15.
Stripline Z = [60 / sqrt(Er)] * ln{4H / [0.67Ï€(T + 0.8W)]}, where H is the distance between the two reference planes, and the trace is in the middle. This formula applies when W/H < 0.35 and T/H < 0.25.
18. Can a ground wire be added in the middle of a differential signal line?
No, a ground wire cannot be added in the middle of a differential signal line. The main benefit of differential signals is mutual coupling, such as flux cancellation and noise immunity. Adding a ground wire would destroy this coupling effect.
19. Does rigid-flex board design require special design software and specifications? Where can I find this type of circuit board processing in China?
Flexible printed circuits can be designed using standard PCB software. The same is true for FPC manufacturers using Gerber format. Due to different manufacturing processes, each manufacturer has restrictions on minimum line width, spacing, and aperture based on their capabilities. Some copper can be reinforced at the turning points of flexible circuits. Manufacturers can be found online using the keyword "FPC."
20. What are the principles for properly selecting the PCB and case grounding points?
The principle of selecting the PCB and case grounding points is to use chassis ground to provide a low-impedance path for return current and control this return current. For example, the PCB ground plane can be connected to the chassis ground using a fixed screw near the high-frequency device or clock generator to minimize the entire current loop area and reduce electromagnetic radiation.
21. What aspects should be considered when debugging a circuit board?
In digital circuits, first verify three things: 1. Ensure all power supply values are within the design requirements. Some systems with multiple power supplies may require specific order and speed for some power supplies. 2. Verify that all clock signal frequencies are working properly and that there are no non-monotonic problems on the signal edges. 3. Verify that the reset signal meets the specifications. If these are normal, the chip should signal the first cycle. Next, follow the system operation principle and bus protocol for debugging.
22. When the circuit board size is fixed, and more functions need to be accommodated, increasing trace density may lead to increased mutual interference. How to address this in high-speed (>100MHz) high-density PCB design?
Crosstalk interference is a major concern in high-speed, high-density PCB design. Here are some tips:
Control the continuity and matching of the trace characteristic impedance.
Maintain proper trace spacing, typically twice the line width. Use simulation to understand the impact of spacing on timing and signal integrity.
Choose appropriate termination methods.
Avoid the same direction of upper and lower adjacent layers, even if traces overlap exactly above and below, as this increases crosstalk.
Use blind/buried vias to increase trace area, though this increases PCB manufacturing costs. Try to achieve full parallelism and equal length.
Reserve differential and common-mode termination to mitigate effects on timing and signal integrity.
23. Why is LC filtering sometimes worse than RC filtering?
The comparison of LC and RC filtering effectiveness depends on the frequency band and inductance value selected. Inductors are related to inductance and frequency. If the noise frequency is low and the inductance value is insufficient, the filtering effect may be worse than RC. However, RC filtering consumes energy and is inefficient, so the resistor must withstand the selected power.
24. How to choose inductor values when filtering, what is the method for determining capacitance values?
In addition to considering the noise frequency to filter, consider the response capability of the instantaneous current. If the LC output can produce a large current instantaneously, a large inductor value may hinder the current flow and increase ripple noise. Capacitor value is related to the acceptable ripple noise level. The smaller the ripple noise, the larger the capacitance. ESR/ESL of the capacitor also affects performance. If the LC is placed at the output of a switching regulator, note the pole/zero effect on the feedback loop stability.
25. How to achieve EMC requirements without causing excessive cost pressure?
EMC-related costs often arise from increased shielding and suppression of high-frequency harmonics like ferrite beads and chokes. It is usually necessary to match the shielding structure of other mechanisms to ensure the system passes EMC requirements. Here are a few PCB design techniques to reduce electromagnetic radiation:
Use devices with slower slew rates to reduce high-frequency components.
Position high-frequency devices away from external connectors.
Ensure impedance matching for high-speed signals, trace layer, and return current path to reduce high-frequency reflections and radiation.
Place enough decoupling capacitors on the power pins of each device to mitigate noise on the power and ground planes. Pay particular attention to the frequency response and temperature characteristics of the capacitor.
Segment the ground near the external connector and connect the connector ground to the chassis ground.
Use ground guard/shunt traces for very high-speed signals, but be mindful of their effect on trace characteristic impedance.
Keep the power plane 20H less than the ground plane, where H is the distance between the power and ground planes.
26. When there are multiple digital/analog function blocks on a PCB, the conventional practice is to separate digital and analog grounds. Why?
Separating digital and analog grounds prevents noise generated by the digital circuit from interfering with the analog circuit. Digital circuits generate noise at the power supply and ground when switching between high and low potentials. If the ground plane is not divided and the noise from the digital area is large, the analog circuit may still be disturbed even if digital-analog signals do not cross. This method is only suitable when the analog area is far from the digital area generating large noise.
27. Another method is to ensure that the digital/analog layout is separated, and the digital/analog signal traces do not cross each other, with the entire PCB not divided and the digital/analog ground connected to the ground plane. Is this accurate?
The requirement that digital-analog signal traces cannot cross is because digital signals with slightly higher speeds return to the source along the ground near the lower side of the trace. When crossed, the noise from the return current appears in the analog circuit area.
28. How to consider impedance matching when designing high-speed PCB schematics?
Impedance matching is an essential element in high-speed PCB design. The impedance value has an absolute relationship with the routing method, such as surface layer (microstrip) or inner layer (stripline/double stripline), distance from the reference layer (power or ground), trace width, PCB material, etc. Both will affect the characteristic impedance value of the trace. That is, the impedance value can be determined after routing. General simulation software may not consider some non-continuous wiring conditions due to limitations in the line model or mathematical algorithms. At this time, only some terminators, such as series resistors, can be reserved on the schematic. Moderate the effect of discontinuity in the trace impedance. The only way to solve the problem is to pay attention to avoiding impedance discontinuities.
29. Where can I get a more accurate IBIS model library?
The accuracy of the IBIS model directly affects the simulation results. Basically, IBIS can be regarded as the electrical characteristic data of the actual chip I/O buffer equivalent circuit. It can be converted from SPICE models (can also use measurements, but more restrictions), while SPICE data and chip manufacturing have an absolute relationship, so the same device provided by different chip manufacturers has different SPICE data, and the data in the converted IBIS model will also differ. That is to say, if the A manufacturer's devices are used, only they have the ability to provide accurate model data for their devices, because no one else knows better than them what process their devices are made of. If the IBIS provided by the manufacturer is inaccurate, the fundamental solution is to continuously ask the manufacturer to improve.
30. In high-speed PCB design, should designers consider the rules of EMC and EMI from those aspects?
In general EMI/EMC design, both radiated and conducted aspects need to be considered. The former belongs to the higher frequency part (>30MHz) and the latter is the lower frequency part (<30MHz). So you can't just focus on the high frequency and ignore the low frequency part. A good EMI/EMC design must be based on the location of the device, the layout of the PCB stack, the important way to move the device, the choice of the device, etc. If these are not better arranged beforehand, afterwards it will take half the effort and increase the cost. For example, the position of the clock generator should not be close to the external connector. The high-speed signal should go as far as possible to the inner layer and pay attention to the characteristic impedance matching and the continuity of the reference layer to reduce the reflection. The slope of the signal pushed by the device (slew rate) should be as small as possible to reduce high-frequency components. Choose decoupling/bypass capacitors and pay attention to whether the frequency response meets the requirements to reduce power layer noise. In addition, pay attention to the return path of the high-frequency signal current so that the loop area is as small as possible (that is, the loop impedance is as small as possible) to reduce the radiation. It is also possible to divide the formation to control the range of high-frequency noise. Finally, properly select the chassis ground of the PCB and the enclosure.
31. How to choose EDA tools?
In the current PCB design software, thermal analysis is not a strong point, so it is not recommended. Other functions 1.3.4 can choose PADS or Cadence with a good price-performance ratio. Beginners of PLD design can use the integrated environment provided by PLD chip manufacturers, and single-point tools can be used when designing more than one million gates.
32. Please recommend an EDA software suitable for high-speed signal processing and transmission.
With conventional circuit design, INNOVEDA's PADS is very good, and there are simulation software that works together, and this type of design often occupies 70% of applications. In high-speed circuit design, analog and digital hybrid circuits, Cadence's solution should be a relatively good performance software. Of course, Mentor's performance is still very good, especially its design process management should be the best. (Da Tang Telecom Technology Expert Wang Sheng)
33. What is the meaning of the various layers of the PCB?
Topoverlay - the name of the top device, also known as top silkscreen or top component legend, such as R1 C5, IC10. Bottomoverlay--common multi-layer--If you design a 4-layer board, you place a free pad or via, define it as multilay, then its pad will automatically appear on 4 layers, if you only define it Top layer, then its pad will only appear on the top layer.
34. What should be paid attention to in routing, typesetting, and other aspects for high-frequency PCB design above 2G?
High-frequency PCBs above 2G are RF circuit designs and are not covered by high-speed digital circuit design. The layout and routing of the RF circuit should be considered together with the schematic, as the layout will cause a distribution effect. Moreover, the RF circuit design of some passive components is realized by parameterized definition, special shape copper foil, so EDA tools are required to provide parametric devices and to edit special shape copper foil. Mentor's boardstation has dedicated RF design modules to meet these requirements. Moreover, general RF design requires specialized RF circuit analysis tools. The industry's best known is Agilent's EESOFT, which has a good interface with Mentor's tools.
35. For a high-frequency PCB design of 2G or higher, what rules should be followed in the design of microstrip?
RF microstrip line design requires 3D field analysis tools to extract transmission line parameters. All rules should be specified in this field extraction tool.
36. For a full digital signal PCB, there is an 80MHz clock source on the board. In addition to the use of wire mesh (grounding), what circuit should be used to protect it in order to ensure sufficient driving capability?
To ensure that the drive capability of the clock should not be achieved through protection, a clock driver chip is generally used. The general concern about clock drive capability is due to multiple clock loads. Using a clock driver chip, a clock signal is turned into several, using a point-to-point connection. Select the driver chip, in addition to ensuring a basic match with the load, the signal edge meets the requirements (generally the clock is along the valid signal). When calculating the system timing, it is necessary to count the clock delay in the driver chip.
37. If a separate clock signal board is used, what kind of interface is generally used to ensure that the transmission of the clock signal is less affected?
The shorter the clock signal, the smaller the transmission line effect. Using a separate clock signal board increases the signal routing length. Moreover, the grounding power supply of the board is also a problem. For long-distance transmission, a differential signal is recommended. The LVDS signal can meet the drive capability requirements, but your clock is not too fast and not necessary.
38. For a 27M, SDRAM clock line (80M-90M), the second and third harmonics of these clock lines are just in the VHF band, and the interference is very high after the high-frequency input from the receiving end. In addition to shortening the line length, what better way?
If the third harmonic is large, the second harmonic is small, probably because the signal duty cycle is 50%, because in this case, the signal has no even harmonics. At this time, you need to modify the signal duty cycle. In addition, for a clock signal that is unidirectional, source-side series matching is generally used. This suppresses secondary reflections but does not affect the clock edge rate. The source matching value can be obtained by the formula below.
39. What is the topology of the trace?
Topology, some is also called routing order, the routing order for networks with multi-port connections.
40. How to adjust the topology of the trace to improve signal integrity?
This kind of network signal direction is more complicated, because the unidirectional, bidirectional signal, different level signal, the topology effect is different, it is difficult to say which topology is beneficial to the signal quality. Moreover, when doing pre-simulation, what kind of topology is used is very demanding for engineers, and it is required to understand the circuit principle, signal type, and even wiring difficulty.
41. How to reduce the EMI problem by arranging the laminate?
First of all, EMI should be considered from the system, and the PCB alone cannot solve the problem. For EMI, I think it is mainly to provide the shortest return path of the signal, reduce the coupling area, and suppress differential mode interference. In addition, the ground layer is tightly coupled to the power layer, which is more suitable than the power layer to suppress common mode interference.
42. Why do you want to lay copper?
There are several reasons for copper plating. 1, EMC. For a large area of ground or power copper, it will play a shielding role, and some special, such as PGND to protect. 1, PCB process requirements. Generally, in order to ensure the plating effect, or the laminate is not deformed, copper is laid for the PCB layer with less wiring. 3, signal integrity requirements, give a high-frequency digital signal a complete return path, and reduce the wiring of the DC network. Of course, there are heat dissipation, special device installation requires copper plating and so on.
43. In a system, including DSP and PLD, what problems should I pay attention to when wiring?
Look at the ratio of your signal rate to the length of the wiring. If the signal is comparable to the time delay of the transmission line and the time of the signal change, consider the signal integrity problem. In addition, for multiple DSPs, clocks, data signal traces will also affect signal quality and timing, and need attention.
44. In addition to Protel tool wiring, are there other good tools?
As for the tools, in addition to PROTEL, there are many wiring tools, such as MENTOR's WG2000, EN2000 series and powerpcb, Cadence's allegro, Zuken's cadstar, cr5000, etc., each with its own strengths.
45. What is the “signal return path�
Signal return path, that is, return current. When a high-speed digital signal is transmitted, the signal flows from the driver along the PCB transmission line to the load, and then the load returns to the driver through the shortest path along the ground or power source. This return signal on the ground or power supply is called the signal return path. Dr. Johnson explained in his book that high-frequency signal transmission is actually the process of charging the dielectric capacitor between the transmission line and the DC layer. SI analyzes the electromagnetic properties of this paddock and the coupling between them.
46. How to perform SI analysis on the connector?
In the IBIS 3.2 specification, there is a description of the connector model. The EBD model is generally used. If it is a special board, such as a backplane, a SPICE model is required. Multi-board simulation software (HYPERLYNX or IS_multiboard) can also be used. When building a multi-board system, the distribution parameters of the input connectors are generally obtained from the connector manual. Of course, this method will not be accurate enough, but as long as it is within an acceptable range.
47. What are the methods of termination?
Terminal, also known as matching. The active end matching and the terminal matching are generally classified according to the matching position. The source-side matching is generally a series matching of resistors. The terminal matching is generally parallel matching. There are many ways, such as resistance pull-up, resistor pull-down, Dyvenan matching, AC matching, and Schottky diode matching.
48. What is the factor of termination (matching)?
The matching mode is generally determined by the BUFFER characteristics, the topology, the type of the level, and the decision mode. The duty cycle of the signal and the power consumption of the system are also considered.
49. What are the rules for using termination (matching)?
The most critical aspect of digital circuits is the timing problem. The purpose of the matching is to improve the signal quality and obtain a determinable signal at the decision time. For the level effective signal, the signal quality is stable under the premise of ensuring the establishment and holding time; for the delay effective signal, the signal change delay speed meets the requirements under the premise of ensuring the signal delay monotonicity. Some information about matching is available in the Mentor ICX product textbook. In addition, "High Speed Digital design a handbook of blackmagic" has a chapter dedicated to the terminal, from the electromagnetic wave principle to describe the role of matching on signal integrity, for reference.
50. Can I simulate the logic function of the device using the IBIS model of the device? If not, how do you perform board level and system level simulation of the circuit?
The IBIS model is a behavioral model and cannot be used for functional simulation. Functional simulation requires a SPICE model or other structural level model.
51. In the system where digital and analog coexist, there are 2 kinds of processing methods, one is to separate the digital ground and the analog ground. For example, in the ground layer, the digital ground is an independent piece, and the analog ground is independent. The single point is copper or FB magnetic. The beads are connected, and the power supply is not separated; the other is that the analog power supply and the digital power supply are connected separately by FB, and the ground is uniformly. May I ask Mr. Li, are the two methods the same effect?
It should be said that it is the same in principle. Because the power supply and ground are equivalent to high frequency signals.
The purpose of distinguishing the analog and digital parts is to prevent interference, mainly the interference of digital circuits to analog circuits. However, the segmentation may cause the signal return path to be incomplete, affecting the signal quality of the digital signal and affecting the system EMC quality. Therefore, no matter which plane is divided, it depends on whether the signal return path is increased and how much the recirculation signal interferes with the normal working signal. There are also some hybrid designs, regardless of the power supply and ground. In the layout, the layout is separated according to the digital part and the analog part to avoid cross-region signals.
52. Safety issues: What is the specific meaning of FCC and EMC?
FCC: Federal Communication Commission. EMC: Electromagnetic Compatibility. Electromagnetic compatibility. FCC is a standards organization and EMC is a standard. Standards are issued with corresponding reasons, standards and test methods.
53. What is differential wiring?
Differential signals, some of which are also called differential signals, use two identical signals with opposite polarities to transmit one channel of data, relying on the difference between the two signal levels. In order to ensure that the two signals are completely consistent, parallelism should be maintained during wiring, and the line width and line spacing remain unchanged.
54. What are the PCB simulation software?
There are many types of simulations, and high-speed digital circuit signal integrity analysis and simulation (SI) commonly used software are ICX, SignalVision, HyperLynx, XTK, SpeectraQuest, and so on. Some also use HSPICE.
55. How does the PCB simulation software perform LAYOUT simulation?
In high-speed digital circuits, in order to improve signal quality and reduce wiring difficulty, a multi-layer board is generally used to allocate a dedicated power layer and a ground layer.
56. How to deal with the layout and wiring to ensure the stability of signals above 50M?
The key to high-speed digital signal routing is to reduce the impact of the transmission line on signal quality. Therefore, the high-speed signal layout above 100M requires the signal trace to be as short as possible. In digital circuits, high-speed signals are defined by the signal rise time. Moreover, different types of signals (such as TTL, GTL, LVTTL), the method of ensuring signal quality is different.
57. The RF part of the outdoor unit, the IF part, and even the low-frequency circuit part that monitors the outdoor unit are often deployed on the same PCB. What are the requirements on the material of such a PCB? How to prevent interference between RF, IF and even low frequency circuits?
Hybrid circuit design is a big problem. It's hard to have a perfect solution.
Generally, the RF circuit is laid out as a separate single board in the system, and even a special shielding cavity is provided. Moreover, the RF circuit is generally single-sided or double-sided, and the circuit is relatively simple, all of which are designed to reduce the influence on the distribution parameters of the RF circuit and improve the consistency of the RF system. Compared with the general FR4 material, the RF circuit board tends to be a substrate with a high Q value. The dielectric constant of this material is relatively small, the transmission line distribution capacitance is small, the impedance is high, and the signal transmission delay is small. In the hybrid circuit design, although the RF and digital circuits are on the same PCB, they are generally divided into a RF circuit area and a digital circuit area, and are respectively arranged and routed. Shielded between grounded vias and shielded boxes.
58. For the RF part, the IF part and the low frequency circuit part are deployed on the same PCB. What solution does the mentor have?
Mentor's board-level system design software includes a dedicated RF design module in addition to basic circuit design features. In the RF schematic design module, a parametric device model is provided, and a bidirectional interface with an RF circuit analysis simulation tool such as EESOFT is provided; in the RF LAYOUT module, a pattern editing function dedicated to the layout of the RF circuit is provided, and the bidirectional interface of the RF circuit analysis and simulation tool such as EESOFT can reverse the schematic and PCB for the analysis and simulation results. At the same time, with the design management function of Mentor software, design reuse, design derivation, and collaborative design can be easily realized. Greatly accelerate the hybrid circuit design process. Mobile phone boards are typical hybrid circuit designs, and many large mobile phone design manufacturers use Mentor and Agilent's EESOFT as the design platform.
59. On a 12-layer PCB board, there are three power layers: 2.2V, 3.3V, and 5V. Should each of the three power layers be placed on one layer, and how should the ground be handled?
Generally speaking, placing the three power layers on three separate layers is better for signal quality. Because it is unlikely to encounter signal plane segmentation phenomena. Plane segmentation is a critical factor affecting signal quality, and simulation software often ignores it. For power and ground layers, they are equivalent to high-frequency signals. In practice, in addition to considering signal quality, power plane coupling (using adjacent ground planes to reduce power plane AC impedance) and layer symmetry are also factors to consider.
60. How does the PCB check whether it meets the design process requirements when it is shipped?
Many PCB manufacturers perform an electrical network continuity test before shipping to ensure all connections are correct. Additionally, more manufacturers now use X-ray testing to check for faults during etching or lamination. For finished boards after SMT, ICT testing is generally used, which requires adding ICT test points during PCB design. If there are issues, a special X-ray inspection device can be used to determine if the fault is due to manufacturing.
61. When choosing chips, should we also consider the ESD issue of the chip itself?
Whether it's a double-layer board or a multi-layer board, try to increase the ground area. When choosing chips, consider the ESD characteristics of the chip itself, which are usually mentioned in the chip documentation. Even chips from different manufacturers of the same type may have different performances. Designing with care and being comprehensive can ensure the performance of the circuit board. However, ESD issues may still occur, so institutional protection is also very important for ESD protection.
62. When making a PCB, should the ground be formed into a closed loop to reduce interference?
When making a PCB, it is generally advisable to reduce the loop area to minimize interference. When laying out the ground, it is better to use a tree-like layout rather than a closed loop, and also try to increase the ground area as much as possible.
63. If the simulator uses one power supply and the PCB uses another power supply, should the two power supplies share a ground?
If it is possible to use separate power supplies, it is better, as this reduces interference between power supplies. However, most devices have specific requirements. Since the simulator and PCB use two power supplies, in my opinion, they should not be grounded together.
64. If a circuit consists of several PCBs, should they share a ground?
If a circuit consists of several PCBs, it is usually required to share a ground, as using multiple power supplies is not practical. However, if you have the specific conditions, using different power supplies can reduce interference.
65. Designing a handheld product with an LCD, metal casing. During ESD testing, it failed to pass the ICE-1000-4-2 test, with contact only passing 1100V and air passing 6000V. During ESD coupling testing, horizontal could only pass 3000V and vertical could pass 4000V. CPU frequency is 33MHz. What methods can be used to pass ESD testing?
Handheld products with metal casings face significant ESD issues, and LCDs may also show many defects. If it's impossible to change the existing metal material, it is recommended to add anti-static materials inside the mechanism, strengthen the PCB ground, and find a way to ground the LCD. How to operate depends on the specific situation.
66. When designing a system with DSP and PLD, what aspects should be considered for ESD?
For general systems, the main consideration is the parts directly touched by the human body, and appropriate protection should be implemented on the circuit and in the mechanism. As for how much ESD affects the system, it depends on the situation. In dry environments, ESD phenomena are more severe, and more sensitive systems are more affected. Although large systems may not be significantly affected by ESD, design should still be careful and take preventive measures.
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