Seven-bit parallel serial code conversion circuit principle

As shown in the figure, IC (555) and R:, RP1, and C1 form a rentless multivibrator, generating a pulse of f=1.44/(R1 十RPl)Cl, which is added to the CL of IC2 and IC3-2 as a clock. end. IC3 is a double D flip-flop 74LS74. The added start pulse makes the Q of IC3-1 low, so that the LD of the IC2 shift register is also low, and the parallel code D.~D6 is registered therein. Register Q.~Q6. With the shifting clock of IC1, the registered code is sequentially shifted to Q7, and the output terminal Q of IC3-2 is removed.

Seven-bit parallel serial code conversion circuit



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