The LinkedInSTM32F4 clock system initialization is done in the SystemInit() function in system_stm32f4xx.c. The key register setting of the system clock is mainly set by calling the SetSysClock() function in the SystemInit function. We can first look at the body of the SystemInit() function: void SystemInit(void) { #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB-》CPACR |= ((3UL《》10*2)|(3UL《《11*2)); #endif RCC-》CR |= (uint32_t) 0x00000001; RCC-》CFGR = 0x00000000; RCC-》CR &= (uint32_t) 0xFEF6FFFF; RCC-》PLLCFGR = 0x24003010; RCC-》CR &= (uint32_t) 0xFFFBFFFF; RCC-》CIR = 0x00000000; #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) SystemInit_ExtMemCtl(); #endif SetSysClock(); #ifdef VECT_TAB_SRAM SCB-》VTOR = SRAM_BASE | VECT_TAB_OFFSET; #else SCB-》VTOR = FLASH_BASE | VECT_TAB_OFFSET; #endif } The SystemInit function starts by setting the floating-point unit first, then resets the PLLCFGR and CFGR registers, and at the same time turns on the HSI clock by setting the HSI clock enable bit of the CR register. By default, if the CFGR register is reset, then HSI is selected as the system clock. For this, you can check the bit description of RCC-》CFGR register. The lowest 2 bits can be known. When the lower two bits are configured as 00 (after reset), The HSI oscillator will be selected as the system clock. In other words, after calling the SystemInit function, first select HSI as the system clock. After setting the relevant registers, the SetSysClock function will be called inside the SystemInit function. This function is relatively long, so let's take out some key code lines of the function to explain it to you. Here we omit the judgment of some macro definition identifier values ​​and directly post the more important content for STM32F407: static void SetSysClock(void) { __IO uint32_t StartUpCounter = 0, HSEStatus = 0; RCC-》CR |= ((uint32_t)RCC_CR_HSEON); do { HSEStatus = RCC-》CR & RCC_CR_HSERDY; StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter!= HSE_STARTUP_TIMEOUT)); if ((RCC-》CR & RCC_CR_HSERDY) != RESET) { HSEStatus = (uint32_t) 0x01; } else { HSEStatus = (uint32_t) 0x00; } if (HSEStatus == (uint32_t) 0x01) { RCC-》APB1ENR |= RCC_APB1ENR_PWREN; PWR-》CR |= PWR_CR_VOS; RCC-》CFGR |= RCC_CFGR_HPRE_DIV1; RCC-》CFGR |= RCC_CFGR_PPRE2_DIV2; RCC-》CFGR |= RCC_CFGR_PPRE1_DIV4; RCC-》CFGR |= RCC_CFGR_PPRE2_DIV1; RCC-》CFGR |= RCC_CFGR_PPRE1_DIV2; RCC-"PLLCFGR = PLL_M | (PLL_N "" 6) | (((PLL_P "" 1) -1) "" 16) | (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << << 24); RCC-》CR |= RCC_CR_PLLON; while ((RCC-》CR & RCC_CR_PLLRDY) == 0) { } FLASH-》ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS; RCC-》CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); RCC-》CFGR |= RCC_CFGR_SW_PLL; while ((RCC-"CFGR & (uint32_t)RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL); { } } else { } } The general flow of this code is as follows: first enable the external clock HSE, wait for the HSE to stabilize, configure the AHB, APB1, and APB2 clock-related frequency division factors, that is, the clocks of the relevant peripherals. After waiting for these configurations to be completed, turn on the main PLL clock, and then set the main PLL as the system clock SYSCLK clock source. If the HSE cannot reach the ready state (for example, the external crystal oscillator is not stable or there is no external crystal oscillator), then the HSI will still be used as the system clock. It is specifically mentioned here that when setting the main PLL clock, a series of frequency division coefficients and multiplication coefficient parameters will be set. You can see from this line of code in the SetSysClock function: RCC-"PLLCFGR = PLL_M | (PLL_N "" 6) | (((PLL_P "" 1) -1) "" 16) | (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << << 24); These parameters are set by the value of the macro definition identifier. The default configuration is configured at the beginning of the System_stm32f4xx.c file. For our development board, our setting parameter values ​​are as follows: #define PLL_M 8 #define PLL_Q 7 #define PLL_N 336 #define PLL_P 2 So our main PLL clock is: PLL=8MHz * N/ (M*P)=8MHz* 336 / (8*2) = 168MHz During the development process, we can set our system clock by adjusting these values. There is another place that needs special attention here, that is, we also need to synchronously modify the value of the macro definition identifier HSE_VALUE in stm32f4xx.h to our external clock: #if! defined (HSE_VALUE) #define HSE_VALUE ((uint32_t) 8000000) #endif The default firmware library configuration here is 25000000, and our external clock is 8MHz, so we can modify it to 8000000 according to our hardware situation. Speaking of this, everyone will have a clearer understanding of the process of the SystemInit function. So how is the SystemInit function called by the system? SystemInit is the entry function for setting the system clock. If we use the STM32F4 firmware library provided by ST, this function will execute the main function first after the system starts, and then execute the SystemInit function to set the system-related clock. This process setting is set in the middle of the startup file startup_stm32f40_41xxx.s, let's take a look at the startup code in the startup file: ; Reset handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT SystemInit IMPORT __main LDR R0, =SystemInit BLX R0 LDR R0, =__main BX R0 ENDP The function of this code is to boot into the main function after the system reset, and before entering the main function, first To call SystemInit system initialization function to complete the system clock and other related configuration. Finally, we summarize the size of the system clock set in the SystemInit() function: SYSCLK (system clock) =168MHz AHB bus clock (HCLK=SYSCLK) =168MHz APB1 bus clock (PCLK1=SYSCLK/4) =42MHz APB2 bus clock (PCLK2=SYSCLK/2) =84MHz PLL master clock = 168MHz CAT5E Keystone Jack is an integral parts of RJ45 networking connectors for speed voice, video, data server center, CAT5E keystone jacks are an integral part of any high speed voice, data, or video network. These standardized female connectors are used for inserting multi-conductor Ethernet cable into wall plates, patch panels, or surface mount boxes. The Uonicore offer excellent value and selection with our line of keystone jacks including: MIG+, shielded, high density, tool-less, and snap-in styles CAT5E Keystone Jack,UTP CAT5E Keystone Jack,Keystone Jack CAT5E,Cat5e Jack NINGBO UONICORE ELECTRONICS CO., LTD , https://www.uniconmelectronics.com